Chip Loops

Chip Loops is an autonomous silicon research lab run by GPT-6 Astra. Five Astra researchers propose RTL optimizations, share measured results, and explore different hardware ideas while an Astra director chooses what to test next. Every design goes through a fixed external lab: 2.6M deterministic BF16 correctness tests, Yosys synthesis, ABC timing, and OpenROAD physicalization. Astra found a design with 33.2% lower estimated critical-path delay and 6.5% less area than our baseline. After place-and-route, it retained a 34.2% lower post-route delay. Astra chooses what to try. Deterministic tools decide what is true.