Crusoe Forge

Crusoe Forge is an agent that speeds up FPGA designs. You give it a slow Verilog design and a target clock speed for a Lattice ECP5 chip. It rewrites the code, runs a testbench to prove the new version still gives the right answers, and measures the real speed with the open-source chip tools (Yosys and nextpnr). If it misses the target, it reads the slowest path in the design, looks up vendor docs with You.com, and tries again. It throws out any fix that breaks the design, and any citation whose page doesn't actually back it up. After each run, a reflector writes down what worked in a playbook that the next run reads first. A meta loop then checks whether those lessons really helped, and removes any that can't show a measured benefit. The problem: making a design fast enough on an FPGA ("timing closure") is slow, expert work, and AI tools tend to hand you code that's fast but wrong. Here the real tools decide, not the model. Results from today: - A 32x32 multiply-accumulate went from 73.9 to 208.1 MHz with the testbench passing. - An 8-tap FIR filter went from 66.59 to 138.64 MHz. - Asked for 250 MHz, the agent checked the datasheet's 225 MHz DSP limit and lowered the target to 207 MHz instead of chasing a number the chip can't reach. The same prompt also produces a Mandelbrot core that matches the reference on all 307,200 pixels, an HDMI add-on PCB with 0 DRC errors, and a parts list priced live from distributor pages. What we can't claim: we couldn't show that the learned lessons help yet. Run-to-run noise was bigger than the effect, so the meta loop rolled them back. hackcore/ (the API wrappers) was built the night before the event and is disclosed as pre-event plumbing.