SruSan

Kaaval is an AI design reviewer for analog chip designs. It catches the bugs that only show up when the chip powers on, before the chip is made. The problem: an analog block is usually simulated on its own, with every supply already on. On a real chip the rails come up in some order and at some speed, and the output drives a pad and a board. A circuit can pass every simulation its designer ran and still come up dead on silicon. Open-silicon shuttles check layout rules, not this. A dead chip costs a shuttle slot and months of waiting. It is getting worse. In the Siemens / Wilson Research Group study, only 14 % of chip projects worked on first silicon in 2024 (about 30 % historically), and 5 % in 2026. Analog is the second most common cause of a respin, and analog tuning was cited in 41 % of respins in 2020. Catching these bugs takes a senior analog reviewer, and there are far too few, so most open-silicon designs are never reviewed. How Kaaval works: 1. Upload a design (zip or repo link). Kaaval rebuilds every circuit from its schematics as text; nothing in the repo is executed. 2. Muse Spark reads the design and plans the tests the designer never ran: power-up, stability, power-up order across rails, cross-domain overstress, pad drive. Plans are strict JSON, checked by the engine. 3. ngspice proves each finding on sky130 at 45 conditions (5 process corners × 3 temperatures × 3 supplies), with the waveform, the condition grid and a deck anyone can re-run. 4. Muse Spark designs the fix, such as a missing start-up circuit or new transistor sizes. Kaaval re-simulates it at all 45 conditions and shows it only if it passes everywhere. It also checks layout against schematic (Magic + Netgen), shows a chip view and a 3D view of the real layout, answers questions with citations, and runs in CI as a GitHub Action and as an MCP server. Measured: - Our reference stays at 0 µA at 30 of 45 conditions, while DC analysis says it works at every one. - Muse Spark designed its start-up circuit: proven at 45 of 45 conditions, working current within 1.9 % of the original. - Muse Spark's sizing fix: saturated at 45 of 45 conditions. - On a second tile with 1.8 V and 3.3 V rails, Muse Spark's plans found an oscillator that stops at 21 of 45 conditions, a reference dead when 3.3 V comes up first, a 1.8 V transistor seeing 3.30 V and a 50 kΩ output that sags under the board. - Silicon backtest on 28 real Tiny Tapeout analog chips with lab outcomes (development set): 3 of the 7 in-scope failures flagged by the rule of their failure; 6 of 21 working chips have a design-risk finding. Pre-silicon simulation on open PDKs, not foundry sign-off. The goal: no chip should come back dead for a bug a simulation could have shown.