SiliconMind

SiliconMind lets Muse Spark design part of a 4-bit AI chip, with the LLM that will run on that chip in the loop. NVFP4 dot-product units multiply 4-bit numbers cheaply, but they still sum the results in a wide floating-point accumulator. How narrow can that adder get before Llama gets worse? The agent controls the accumulator width, the width block sums are rounded to before they are added, and the rounding mode. It has three tools: Llama-3.2-1B perplexity measured on a bit-exact emulator of the candidate chip (expensive, 10 calls), Yosys synthesis area, and Verilog verification against an exact reference. After each round it also sees the area-vs-accuracy plot as an image. Muse Spark cut the accumulator by 46% (21,486 → 11,520 transistors; −45% in sky130 cell area), and perplexity on held-out text was unchanged (−0.13%). In four independent runs, it found a smaller accumulator than every baseline with the same 10-evaluation budget: random search, a coarse grid, and Bayesian optimization (TPE). Without tools, Muse Spark played safe and picked accumulators 39–57% larger, so the tools are what get it to a small design. We then measured all 162 candidates to get the ground truth. The smallest design that is 95% sure to stay within the accuracy budget is exactly the one the agent chose in run 1. The face-value optimum is 3% smaller, but it is within budget in only 73% of bootstrap resamples. Told about that uncertainty, a v2 agent delivered a statistically safe design in 4 of 4 runs. In sky130 the chosen accumulator's critical loop is 39% shorter, and the whole multiply-accumulate unit uses 17% less energy per block on real Llama data. Placed and routed, the whole unit is 19% smaller (DRC and LVS clean), and the smallest of the six designs we routed. It also holds beyond the model it was tuned on: on five open models (Llama 3.2 1B and 3B, Qwen2.5 1.5B and 3B, Mistral 7B) and six zero-shot benchmarks, every 95% interval for the change in average accuracy contains zero. The chosen design is bit-exact all the way down: Python spec → GPU emulator → Verilog → a placed-and-routed sky130 layout. In the Tiny Tapeout flow, precheck is clean, timing is met at 10 MHz, and gate-level simulation matches the spec. In the live demo (https://ehdtjq08.github.io/siliconmind/demo/) you can shrink the chip yourself and watch Llama's answers turn into "$ $ $" once the adder starts truncating.