Team Annihilus

Neural Lab is a pocket AI lab that runs a self-judging brain entirely on the phone. The brain is GIDEON, built on the trinity — Ghost, Molecule, and Black Hole. It catches its own failures: when a run fails, it seals the failure as a ghost, a Meta AI judge tells it what went wrong, the ghost's appeal either redeems it or breaks it into molecules, and the molecules steer the next run away from the same mistake. Overflow collapses into gravity wells. The brain grows without forgetting (function-preserving widening) under a substrate-aware ceiling derived from the device itself, and it exports to C that runs bit-exact on a microcontroller. The Meta Model API is not bolted on — it lives inside the Ghost seal step. Every sealed ghost gets a live judge verdict (Muse Spark) in the thought log, visible in the demo. That is the frontier this pushes: failure-learning without cloud retraining, on a device you already carry. BASE (pre-hackathon, Neural Lab v69 and earlier): the Terrarium 3D brain, the 808-parameter [24→16→16→8] network, the substrate probe and ceiling derivation, the Ghost / Molecule / Black Hole lifecycle, Net2Net growth, the C export + virtual MCU simulator, the guidebook, and the test suite. HACKATHON-NEW (Oct 26–Nov 4): the Meta API judge loop (v70–v75, first live verdict Oct 27); the fullscreen demo view (v76–v78); Dish instruments (v79) — live Events, Seals with judge verdicts, Molecules, Gravity; the swipe deck (v80); the TNEC-1 chip (register map, FreeRTOS SPI driver, RISC-V RV32IMC SoC spec, 360 die viewer); and fly-brain validation on the FlyWire FAFB v783 connectome (3.87M connections): the learned-pattern layer distills 52x at cell-type level and 152x at neuropil level, and identity carried by the record's sealed barrier (the author's design) restored records at 100% with 90% of each fingerprint deleted, where content matching alone falls to 60%. The author also diagnosed the audit's v2 regression from the reported results alone — without reading its code — naming the missing variable (synaptic charge) that became the v3 fix. The architecture's entire learned state at full chip caps is 9,952 bytes. Future work: TNEC-1, a hardware implementation of the trinity lifecycle — verified §3 register map (28 ghost records, 56 molecule fragments), FreeRTOS host SPI driver, RISC-V RV32IMC SoC specification (Wishbone B4, 64 KB weight SRAM) with a sub-2 µs decision loop at 48 MHz. Next: Renode simulation, FPGA prototyping, open-source silicon (Sky130), and TNEC-1 as the main compute chip in a holographic computer.