The veri_good_bugsquashers

We provide an entire end-to-end agentic pipeline for embedded systems which use FPGAs (extendable to CPLDs, etc). Users with no experience in verilog can upload/design their C code and have it converted to verilog with an agent orchestrated to iterate and improve it via synthesis/simulation of an FPGA with full test generation and LUT optimization to fit code on smaller and more affordable devices.