# Rafael Vanca

- **Event:** [Meta Global AI Developer Hackathon](https://cerebralvalley.ai/e/meta-ai-developer-hackathon)
- **When:** Oct 26, 12:00 PM – Nov 4, 9:00 PM (EST)
- **Where:** Online
- **Team:** [Rafael Vanca](https://cerebralvalley.ai/u/RafaelVanca)
- **GitHub:** https://github.com/RafaelMarian/ChipLlama
- **Demo video:** https://youtu.be/TNuwFj-aAUs
- **Gallery:** https://cerebralvalley.ai/e/meta-ai-developer-hackathon/hackathon/gallery
- **Page:** https://cerebralvalley.ai/e/meta-ai-developer-hackathon/hackathon/gallery/295

Firmware bugs are the most expensive bugs in the room: a wrong prescaler or a misconfigured clock ships silently, and you find out on the bench — or in the field. AI chatbots don't help, they guess register values with total confidence and zero accountability.
  ChipLlama flips that deal. You describe what the chip should do in plain English — "Timer1 interrupt every 10 ms, priority 5" — and it generates register-exact C, then proves it: a deterministic reference
  solver computes the right answer, Meta Muse Spark writes the code with real datasheet pages attached as images, the actual Microchip XC16 compiler builds it, a register emulator replays the init sequence, and a rule checker diffs the result against the solver. Anything off — a U1BRG off by one, a wrong ISR name, a PPS conflict — goes back to the model with the exact findings until everything passes. Only then is the code marked VERIFIED and exported as an MPLAB X project. One dashboard covers the whole bring-up loop: Generate (verified drivers), Blocks (visual programming, same checker), Audit (existing code scored with datasheet-cited fixes), Explain (every register access decoded), Pin planner (PPS/JTAG/ICS conflicts + init code), Reverse debug (drop an SFR or scope screenshot — vision transcribes it twice, ChipLlama recomputes every number and names the fault), and Circuit (schematic + live ERC + HAL project + BOM). It already spans PIC24, dsPIC33, PIC18 and PIC32, plus Arduino AVR, STM32 and ESP32 family plugins.

  Proven, not promised: 559 tests green, Timer1/UART1/SPI1 and screenshot debug verified live against the real toolchain. Demo: https://youtu.be/TNuwFj-aAUs · Code (MIT):
  https://github.com/RafaelMarian/ChipLlama

  Where it goes next: deeper family coverage (dsPIC33C, PIC32MK, STM32H7, ESP32-S3/C6, RP2040, AVR Dx) with a family-aware pin planner across all of them; harder peripherals (USB stacks, CAN-FD, Ethernet, motor control tuned from scope shots); true hardware-in-the-loop via PICkit 5 — flash, read back the silicon, verify the prediction against reality; meeting engineers where they live with an MPLAB X plugin, a VS Code extension and a CI action that verifies firmware pull requests; and community rule packs so every board gets its own expert auditor.

## More from Meta Global AI Developer Hackathon

- [Nova 2](https://cerebralvalley.ai/e/meta-ai-developer-hackathon/hackathon/gallery/292)
- [cryptobandit](https://cerebralvalley.ai/e/meta-ai-developer-hackathon/hackathon/gallery/293)
- [Kokobubu](https://cerebralvalley.ai/e/meta-ai-developer-hackathon/hackathon/gallery/294)
- [NAVO](https://cerebralvalley.ai/e/meta-ai-developer-hackathon/hackathon/gallery/296)
- [NEURON TS LABS](https://cerebralvalley.ai/e/meta-ai-developer-hackathon/hackathon/gallery/297)
- [SHAMANTH N P : Sketch World](https://cerebralvalley.ai/e/meta-ai-developer-hackathon/hackathon/gallery/298)

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Markdown version of https://cerebralvalley.ai/e/meta-ai-developer-hackathon/hackathon/gallery/295. Site index for agents: https://cerebralvalley.ai/llms.txt · full text: https://cerebralvalley.ai/llms-full.txt