# Future Tech Industries

- **Event:** [Meta Global AI Developer Hackathon](https://cerebralvalley.ai/e/meta-ai-developer-hackathon)
- **When:** Oct 26, 12:00 PM – Nov 4, 9:00 PM (EST)
- **Where:** Online
- **Team:** [Adrian Badjideh](https://cerebralvalley.ai/u/adrian__glazer)
- **GitHub:** https://github.com/GLAZERadr/DaVINCI-Silicon
- **Demo video:** https://youtu.be/XpB7PjqJsQg
- **Gallery:** https://cerebralvalley.ai/e/meta-ai-developer-hackathon/hackathon/gallery
- **Page:** https://cerebralvalley.ai/e/meta-ai-developer-hackathon/hackathon/gallery/2766

AI can write Verilog in seconds. But how do you know the design actually works?

Before building DaVINCI Silicon, I spoke with six chip and FPGA engineers, from IC design teams in Bandung to a staff engineer at a global semiconductor company.

One thing kept coming up: writing RTL is getting easier, but verification and debugging are still where most of the time goes.

One engineer put it perfectly: "Coding takes a week, debugging takes months."

Another shared how his tests all passed, only to discover they were quietly testing the bypass instead of the actual functionality.

Everything was green, but the important part had never really been tested.

That made us ask: what if AI could write the RTL, but had absolutely no control over how its work was evaluated?

That's what we're building with DaVINCI Silicon.

Here's how it works:

1. Upload a chip specification (PDF or image). Muse Spark extracts the requirements, which a human reviews and approves.
2. DaVINCI creates an independent verification suite and golden model, then freezes them using hashes. AI cannot access or modify the tests.
3. Before generating RTL, we deliberately inject known bugs into a reference design to check whether the tests can actually catch them.
4. Muse Spark generates Verilog, which runs in a real simulator inside a sandbox.
5. If something fails, AI can propose RTL fixes, with a maximum of three attempts. The full regression suite runs after every change.
6. Every run records simulator results, AI calls, failures, and costs, making experiments reproducible.

So, what have we tested?

We started with a synchronous FIFO:

- 10/10 functional requirements verified.
- 8/8 planted bugs detected.
- All defined corner cases exercised.
- 6/6 formal properties proved using SymbiYosys.
- Successfully passed through the open-source SKY130 physical design flow, with clean DRC and LVS.

We also found something important: one AI-generated design passed every functional test but performed worse than our reference implementation in timing.

We didn't call it a success. DaVINCI surfaced the difference.

Where we are now:

- 4 live runs completed.
- 30 model calls, including failed attempts.
- Just $0.68 in model spending.
- Two more blocks (saturating gain stage and round-robin arbiter) with independent, frozen test suites.

We built this using open-source tools: Icarus Verilog, cocotb, Yosys, SymbiYosys, OpenSTA, and OpenROAD/LibreLane.

Our goal is simple: make trustworthy RTL generation and verification more accessible to small engineering teams, university labs, and people exploring chip design.

AI should make hardware development faster. But speed without trustworthy verification is just a faster way to introduce bugs.

That's the problem we're trying to solve with DaVINCI Silicon.

Try the live demo:
https://davinci-silicon-fe.vercel.app/

## More from Meta Global AI Developer Hackathon

- [Project Wayfinder](https://cerebralvalley.ai/e/meta-ai-developer-hackathon/hackathon/gallery/2763)
- [Synteel](https://cerebralvalley.ai/e/meta-ai-developer-hackathon/hackathon/gallery/2764)
- [WardDesk Labs](https://cerebralvalley.ai/e/meta-ai-developer-hackathon/hackathon/gallery/2765)
- [Pitchside](https://cerebralvalley.ai/e/meta-ai-developer-hackathon/hackathon/gallery/2767)
- [Three Billion](https://cerebralvalley.ai/e/meta-ai-developer-hackathon/hackathon/gallery/2768)
- [Doyle](https://cerebralvalley.ai/e/meta-ai-developer-hackathon/hackathon/gallery/2769)

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